The present invention relates generally to a method for fabricating dual damascene structure and in particular relates to a process to avoid the organic dielectric layer damaged by the oxygen-containing plasma.
As feature size of the semiconductor devices has become smaller and multilevel metallization commonplace in integrated circuits, low dielectric constant films have become increasingly important. Unfortunately, as the metal spacing decreases, the interlevel (on the same metal level) and the intralevel (between metal levels) capacitance increase when the insulator having the same dielectric constant (k) is used, since the capacitance C is inversely proportional to spacing d between the conducting lines (C=kxcex50A/d where k is the dielectric constant, xcex50 indicates the permittivity in a vacuum, A is the area, and d is the thickness of the capacitor dielectric). Additionally, the RC delay time is proportional to the capacitance C (R is the resistance of the conducting lines). That is, the electrical property (frequency response) of the semiconductor devices perform badly. Therefore, it is very desirable to minimize the dielectric constant k of the insulator between the conducting lines to reduce the capacitance C, and therefore the RC delay time, where C indicates the interlevel and/or the intralevel capacitance mentioned above.
Generally, one approach to minimize the capacitance C of the multilevel interconnection is to form an organic SOG (spin on glass). It is one dielectric material with low dielectric constant and has a good capability of gap-filling. However, organic SOG is sensitive to moisture and will become unstable when it exposed to oxygen-containing plasma. After damaged by the oxygen-containing plasma, the moisture absorption ability will increase to several order of degree.
One will have the same problem in the process of fabricating the dual damascene structure. There is one traditional dual damascene process described as follows.
Referring to FIG. 1, a liner oxide layer 123, the first insulative layer 130, etching-stop layer 138 are formed in sequence on the substrate 110 with the conducting lines 125. Then, the etching-stop layer 138 is etched with photoresist as a mask having a via image to form a via pattern 135 therein. Next, the second insulative layer 140 is deposited on the etching-stop layer 138.
Subsequently, a photoresist layer (not shown) is formed on the second insulative layer 140 and the photoresist layer is patterned with lithography processes to form trench 150 image therein. Then, the second insulative layer 140 is etched with the photoresist as a mask and meanwhile the first insulative layer 130 is etched with the etching-stop layer 138 as a mask. The result of this etching step is to form a trench 150 in the second insulative layer 140 and a via 135 in the etching stop layer 138, the first insulative layer 130 and the liner oxide layer 123, as shown in the FIG. 2.
Refer to FIG. 3, a metal layer 160 is deposited on the second insulative layer 140 and fill the via 135 and trench 150. And the substrate 110 is processed with chemical mechanical polishing (CMP) until the upper surface of the second insulative layer 140 is exposed. Then, some further steps will be processed on the planarized substrate surface.
As described above, the first insulative layer 130 and the second insulative layer 140 are formed with spin on glass. They will have the problem of moisture-absorption, in particularly, when the organic SOG with low dielectric constant is used. The organic SOG is very sensitive to the moisture. While it exposed to the oxygen-containing plasma, the damaged organic SOG will induce the water-releasing of the organic SOG. This will cause the increasing of the contact resistance and impact the property of the device.
If organic SOG is used as inter-metal dielectric layer in the traditional dual damascene, the adjustment of the dual damascene process is needed to avoid the aforementioned problem. Therefore, one new dual damascene process and structure is provided in present invention to solve the problem.
The present invention provides a manufacturing process for making the sidewall of the organic dielectric layer free from damaged by the oxygen-containing plasma.
Another object of the present invention is to provide a process to avoid the organic dielectric layer releasing moisture to the metal layer.
A further object of the present invention is to provide a method to shorten the RC delay time and to lower the contact resistance.
A pad oxide layer is formed on a substrate with conducting lines and then a barrier layer with the thickness range about 200 to 1000 angstroms is formed on the pad oxide layer by PECVD method. Next, an organic dielectric layer with low dielectric constant is formed on the barrier layer by spinning method and the organic dielectric layer is etched with a patterned the photoresist as a mask and the barrier layer as a etching-stop layer to form trench therein. Then, an anisotropic thickness oxide layer is formed on the substrate by PECVD method. Subsequently, a photoresist layer is formed on the anisotropic thickness oxide layer and the photoresist layer is patterned with lithography processes to form via image therein. Then, the anisotropic thickness oxide layer, the barrier layer and the pad oxide layer are etched with the photoresist as a mask until the conducting line is exposed, and the photoresist layer with the pattern of via is removed by an oxygen-containing plasma. The anisotropic thickness oxide layer of the present invention can protect the organic dielectric layer and prevent from the increasing of the contact resistance. Finally, a metal layer is deposited on the substrate and fills the vias and trenches to form the dual damascene structure.